MVA60041/MA/DP – ZARLINK
1.4 Micron CMOS Megacell ASICs, stacked contacts, dual-layer metal, compiled RAM/ROM/PLA macros, CLA60000-compatible
Stock Quantity: 7127
Selling Unit: Each
| Quantity | Price (ex VAT) |
|---|---|
| 1+ | 9.99 |
| 10+ | |
| 50+ | |
| 100+ |
7127 in stock
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- 6 month warranty on all stock items
- All stock held and shipped from our UK warehouse
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Overview
The MVA60041/MA/DP is a Megacell ASIC from Zarlink Semiconductors, designed for integration of large RAM, ROM, and PLA blocks within high-density digital systems. Based on a 1.1 µm CMOS process with dual-layer metal and stacked contacts, this device supports up to 80,000 usable gates and is netlist-compatible with CLA60000 and CLA70000 gate array families. Its architecture enables efficient routing and compact layout, making it suitable for advanced system-on-chip designs.
Key Features
- Up to 80,000 usable gates
- 1.1 µm channel CMOS process with dual-layer metal
- Compiled macros: ROM (up to 64K bits), RAM (up to 16K bits), and PLAs
- Slew-controlled outputs with 24 mA drive capability
- Netlist compatibility with CLA60000 and CLA70000 families
- ESD protection up to 2 kV
- Maximum junction temperature: 150°C
- Epitaxial silicon for latch-up immunity
Applications
This ASIC is ideal for high-performance embedded systems requiring dense memory integration and analog/digital co-design. Its compatibility and scalability support long-term migration strategies across CMOS platforms.
- System-on-chip integration
- Digital signal processing
- Embedded control systems
- Military-grade electronics
- Custom logic and memory architectures